`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/12/31 20:18:11
// Design Name: 
// Module Name: RDMM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module RDMM(enable,outwait,speed,x0,y0,targetx,targety,x,y,inwait);
	input wire enable;
	input wire outwait;
	input wire speed;
	input wire [9:0] x0;
	input wire [8:0] y0;
	input wire [9:0] targetx;
	input wire [8:0] targety;
	output wire [9:0] x;
	output wire [8:0] y;
    output reg inwait;
    initial inwait = 0;
    
    reg [16:0] hres_bullet_x;
    reg [15:0] hres_bullet_y;
    reg [16:0] tanx;
    reg [15:0] tany;
    reg [2:0] ms;
    
    initial begin
    	hres_bullet_x = x0*128;
    	hres_bullet_y = y0*128;
    	ms = 0;
    end
    assign x = hres_bullet_x[16:7];
    assign y = hres_bullet_y[15:7];
    reg negx_r, negy_r;
    initial negx_r = 0;
    initial negy_r = 0;
    wire xin, yin;
    assign xin = (negx_r)?
    ((hres_bullet_x-tanx<416*128)&&(hres_bullet_x-tanx>=32*128)):((hres_bullet_x+tanx<416*128)&&(hres_bullet_x+tanx>=32*128));
    assign yin = (negy_r)?
    ((hres_bullet_y-tany<463*128)&&(hres_bullet_y-tany>=16*128)):((hres_bullet_y+tany<463*128)&&(hres_bullet_y+tany>=16*128));
    
    always@(posedge speed) begin
    	if (~enable) ms <= 0;
    	if (ms == 0) begin//inactive
    		if (enable) begin
    			inwait <= 0;
    			ms <= 1;
    		end else begin
				hres_bullet_x[16:7]<=x0;
				hres_bullet_y[15:7]<=y0;
    		end
    	end else if (ms == 1) begin//remember
			hres_bullet_x[16:7] <= x0;
			hres_bullet_y[15:7] <= y0;
			if (targetx>x0) begin
				negx_r <= 0;
				tanx <= targetx - x0;
			end else begin
				negx_r <= 1;
				tanx <= x0 - targetx;
			end
			if (targety>y0) begin
				negy_r <= 0;
				tany <= targety - y0;
			end else begin
				negy_r <= 1;
				tany <= y0 - targety;
			end
			ms <= 2;    		
    	end else if (ms == 2) begin
    		if (xin&&yin) begin
				if (negx_r) hres_bullet_x <= hres_bullet_x - tanx;
				else hres_bullet_x <= hres_bullet_x + tanx;
    			if (negy_r) hres_bullet_y <= hres_bullet_y - tany;
    			else hres_bullet_y <= hres_bullet_y + tany;   
    			inwait <= 0; 		    			
    		end else begin
    			inwait <= 1;
    			ms <= 3;
    		end
    	end else if (ms == 3) begin
    		if (outwait) ms <= 1;
    	end
    end
    	/*if (~enable) begin
    		hres_bullet_x[16:7] <= x0;
    		hres_bullet_y[15:7] <= y0;
    		start_state <= 1;
    		out <= 0;
    		waitfor <= 0;
    	else begin
    		
    	end
    	end else begin
    		if (start_state) begin

    		end
			if (~out) begin
				if (xin&&yin) begin
					if (negx_r) hres_bullet_x <= hres_bullet_x - tanx;
					else hres_bullet_x <= hres_bullet_x + tanx;
					if (negy_r) hres_bullet_y <= hres_bullet_y - tany;
					else hres_bullet_y <= hres_bullet_y + tany;    			
				end else begin
					hres_bullet_x <= x0*128;
					hres_bullet_y <= y0*128;
					waitfor <= 1;
					start_state <= 1;
				end
			end
    	end
    end*/
    
endmodule
